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3-1 tm file number 4317.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 HI5662 dual 8-bit, 60msps a/d converter with internal voltage reference the HI5662 is a monolithic, dual 8-bit, 60msps analog-to- digital converter fabricated in an advanced cmos process. it is designed for high speed applications where integration, bandwidth and accuracy are essential. the HI5662 reaches a new level of multi-channel integration. the fully pipeline architecture and an innovative input stage enable the HI5662 to accept a variety of input con?urations, single-ended or fully differential. only one external clock is necessary to drive both converters and an internal band-gap voltage reference is provided. this allows the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. the HI5662 has excellent dynamic performance while consuming only 650mw power at 60msps. the a/d only requires a single +5v power supply and encode clock. data output latches are provided which present valid data to the output bus with a latency of 6 clock cycles. for those customers needing dual channel 10-bit resolution, please refer to the hi5762. for single channel 10-bit applications, please refer to the hi5767. features sampling rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60msps 7.8 bits at f in = 10mhz low power at 60msps. . . . . . . . . . . . . . . . . . . . . 650mw wide full power input bandwidth. . . . . . . . . . . . . 250mhz excellent channel-to-channel isolation . . . . . . . . . >75db on-chip sample and hold ampli?rs internal band-gap voltage reference . . . . . . . . . . . . 2.5v fully differential or single-ended analog inputs single supply voltage operation . . . . . . . . . . . . . . . . +5v ttl/cmos compatible digital inputs cmos compatible digital outputs . . . . . . . . . . . . 3.0/5.0v offset binary digital data output format dual 8-bit a/d converters on a monolithic chip applications wireless local loop psk and qam i and q demodulators medical imaging high speed data acquisition pinout HI5662 (mqfp) top view ordering information part number temp. range ( o c) package pkg. no. HI5662/6in -40 to 85 44 ld mqfp q44.10x10 HI5662eval2 25 evaluation platform 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 a gnd av cc2 id6 id5 id4 id3 dv cc3 d gnd id2 id1 id7 a gnd av cc2 qd6 qd5 qd4 qd3 dv cc3 d gnd qd2 qd1 qd7 id0 nc nc d gnd dv cc1 clk dv cc2 d gnd nc nc qd0 iv dc i in- i in+ a gnd v rin nc v rout av cc1 q in+ q in- qv dc data sheet february 1999
3-2 functional block diagram dv cc3 + - stage 1 stage m-1 clock bias i/qv dc i/q in - i/q in + i/qd0 (lsb) i/qd1 i/qd2 i/qd3 i/qd4 i/qd5 i/qd6 i/qd7 (msb) clk av cc1,2 agnd dv cc1,2 dgnd stage m x2 s/h 2-bit flash 2-bit dac + - x2 2-bit flash 2-bit dac 2-bit flash digital delay and digital error correction reference v refout v refin i or q channel HI5662
3-3 typical application schematic are placed as close 10 f and 0.1 f caps qd7 qd6 qd5 qd4 qd3 qd2 qd1 qd0 bnc clock 10 f 0.1 f10 f + + dgnd agnd (38) v rout (40) v rin clk (17) dgnd (9,15,19,25) (1,33,41) agnd (lsb) qd0 (22) qd1 (23) qd2 (24) qd3 (27) qd4 (28) qd5 (29) qd6 (30) (msb) qd7 (31) (2,32) av cc2 (37) av cc1 dv cc1 (16) to part as possible 0.1 f +5v +5v 0.1 f id7 id6 id5 id4 id3 id2 id1 id0 (lsb) id0 (12) id1 (11) id2 (10) id3 (7) id4 (6) id5 (5) id6 (4) (msb) id7 (3) i in + i in - (43) i in - (42) i in + (44) iv dc 0.1 f10 f + dv cc3 (8,26) +5v or +3v dv cc2 (18) (13,14,20,21,39) nc q in + q in - (35) q in - (36) q in + (34) qv dc HI5662 HI5662
3-4 pin descriptions pin no. name description 1a gnd analog ground 2av cc2 analog supply (+5.0v) 3 id7 i-channel, data bit 7 output (msb) 4 id6 i-channel, data bit 6 output 5 id5 i-channel, data bit 5 output 6 id4 i-channel data bit 4 output 7 id3 i-channel, data bit 3 output 8dv cc3 digital output supply (+3.0v or +5.0v) 9d gnd digital ground 10 id2 i-channel, data bit 2 output 11 id1 i-channel, data bit 1 output 12 id0 i-channel, data bit 0 output (lsb) 13 nc no connect 14 nc no connect 15 d gnd digital ground 16 dv cc1 digital supply (+5.0v) 17 clk sample clock input 18 dv cc2 digital supply (+5.0v) 19 d gnd digital ground 20 nc no connect 21 nc no connect 22 qd0 q-channel, data bit 0 output (lsb) 23 qd1 q-channel, data bit 1 output 24 qd2 q-channel, data bit 2 output 25 d gnd digital ground 26 dv cc3 digital output supply (+3.0v or +5.0v) 27 qd3 q-channel, data bit 3 output 28 qd4 q-channel, data bit 4 output 29 qd5 q-channel, data bit 5 output 30 qd6 q-channel, data bit 6 output 31 qd7 q-channel, data bit 7 output (msb) 32 av cc2 analog supply (+5.0v) 33 a gnd analog ground 34 qv dc q-channel dc bias voltage output 35 q in- q-channel negative analog input 36 q in+ q-channel positive analog input 37 av cc1 analog supply (+5.0v) 38 v rout +2.5v reference voltage output 39 nc no connect 40 v rin +2.5v reference voltage input 41 a gnd analog ground 42 i in+ i-channel positive analog input 43 i in- i-channel negative analog input 44 iv dc i-channel dc bias voltage output pin no. name description HI5662
3-5 absolute maximum ratings t a =25 o c thermal information supply voltage, av cc or dv cc to agnd or dgnd . . . . . . . . . . .6v dgnd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd to dv cc analog i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd to av cc operating conditions temperature range HI5662/6in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) HI5662/6in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations av cc1,2 = dv cc1,2 = +5.0v, dv cc3 = +3.0v; v rin = 2.50v; f s = 60msps at 50% duty cycle; c l = 10pf; t a = 25 o c; differential analog input; unless otherwise speci?d parameter test conditions min typ max units accuracy resolution 8 - - bits integral linearity error, inl f in = 10mhz - 0.5 - lsb differential linearity error, dnl (guaranteed no missing codes) f in = 10mhz - 0.2 1.0 lsb offset error, v os f in = dc -10 - +10 lsb full scale error, fse f in = dc - 1 - lsb dynamic characteristics minimum conversion rate no missing codes - 1 - msps maximum conversion rate no missing codes 60 - - msps effective number of bits, enob f in = 10mhz f in = 10mhz, single ended analog input 7.5 7.0 7.8 7.7 - - bits bits signal to noise and distortion ratio, sinad f in = 10mhz - 48.7 - db signal to noise ratio, snr f in = 10mhz - 48 - db total harmonic distortion, thd f in = 10mhz - -66 - dbc 2nd harmonic distortion f in = 10mhz - -71 - dbc 3rd harmonic distortion f in = 10mhz - -71 - dbc spurious free dynamic range, sfdr f in = 10mhz - 71 - dbc intermodulation distortion, imd f 1 = 1mhz, f 2 = 1.02mhz - 64 - dbc i/q channel crosstalk - -75 -60 dbc i/q channel offset match - 2.5 - lsb i/q channel full scale error match - 2.5 - lsb transient response (note 2) - 1 - cycle over-voltage recovery 0.2v overdrive (note 2) - 1 - cycle rms signal rms noise + distortion -------------------------------------------------------------- = rms signal rms noise ------------------------------- = HI5662
3-6 analog input maximum peak-to-peak differential analog input range (v in + - v in -) - 0.5 - v maximum peak-to-peak single-ended analog input range - 1.0 - v analog input resistance, r in+ or r in- v in+ , v in- = vref, dc - 1 - m ? analog input capacitance, c in+ or c in- v in+ , v in- = 2.5v, dc - 10 - pf analog input bias current, i b + or i b -v in+ , v in- = v ref- , v ref+ , dc (notes 2, 3) -10 - 10 a differential analog input bias current i bdiff = (i b +- i b -) (notes 2, 3) -0.5 - +0.5 a full power input bandwidth, fpbw (note 2) - 250 - mhz analog input common mode voltage range (v in ++ v in -) / 2 differential mode (note 2) 0.25 - 4.75 v internal voltage reference reference output voltage, v rout (loaded) 2.35 2.5 2.65 v reference output current, i rout -24ma reference temperature coefficient - -400 - ppm/ o c reference voltage input reference voltage input, v rin - 2.5 - v total reference resistance, r rin with v rin = 2.5v - 1.25 - k ? reference current, i rin with v rin = 2.5v - 2 - ma dc bias voltage dc bias voltage output, v dc - 3.0 - v maximum output current - - 0.4 ma sampling clock input input logic high voltage, v ih clk 2.0 - - v input logic low voltage, v il clk - - 0.8 v input logic high current, i ih clk, v ih = 5v -10.0 - +10.0 a input logic low current, i il clk, v il = 0v -10.0 - +10.0 a input capacitance, c in clk - 7 - pf digital outputs output logic high voltage, v oh i oh = 100 a; dv cc3 = 5v 4.0 - - v output logic low voltage, v ol i ol = 100 a; dv cc3 = 5v - - 0.8 v output logic high voltage, v oh i oh = 100 a; dv cc3 = 3v 2.4 - - v output logic low voltage, v ol i ol = 100 a; dv cc3 = 3v - - 0.5 v output capacitance, c out -7- pf timing characteristics aperture delay, t ap -5- ns aperture jitter, t aj -5-ps rms data output hold, t h - 10.7 - ns electrical speci?ations av cc1,2 = dv cc1,2 = +5.0v, dv cc3 = +3.0v; v rin = 2.50v; f s = 60msps at 50% duty cycle; c l = 10pf; t a = 25 o c; differential analog input; unless otherwise speci?d (continued) parameter test conditions min typ max units HI5662
3-7 data output delay, t od - 11.7 - ns data latency, t lat for a valid sample (note 2) 6 6 6 cycles power-up initialization data invalid time (note 2) - - 20 cycles sample clock pulse width (low) (note 2) 7.5 8.3 - ns sample clock pulse width (high) (note 2) 7.5 8.3 - ns sample clock duty cycle variation 5% power supply characteristics analog supply voltage, av cc (note 2) 4.75 5.0 5.25 v digital supply voltage, dv cc1 and dv cc2 (note 2) 4.75 5.0 5.25 v digital output supply voltage, dv cc3 at 3.0v (note 2) 2.7 3.0 3.3 v at 5.0v (note 2) 4.75 5.0 5.25 v supply current, i cc f s = 60msps - 130 - ma power dissipation - 650 670 mw offset error sensitivity, ? v os av cc or dv cc = 5v 5% - 0.125 - lsb gain error sensitivity, ? fse av cc or dv cc = 5v 5% - 0.15 - lsb notes: 2. parameter guaranteed by design or characterization and not production tested. 3. with the clock low and dc input. electrical speci?ations av cc1,2 = dv cc1,2 = +5.0v, dv cc3 = +3.0v; v rin = 2.50v; f s = 60msps at 50% duty cycle; c l = 10pf; t a = 25 o c; differential analog input; unless otherwise speci?d (continued) parameter test conditions min typ max units HI5662
3-8 timing waveforms notes: 4. s n : n-th sampling period. 5. h n : n-th holding period. 6. b m , n : m-th stage digital output corresponding to n-th sampled input. 7. d n : final data output corresponding to n-th sampled input. figure 1. HI5662 internal circuit timing figure 2. HI5662 input-to-output timing d n - 6 d n - 5 d n - 1 d n d n + 1 d n + 2 analog input clock input input s/h 1st stage 2nd stage m-th stage data output s n - 1 h n - 1 s n h n s n + 1 h n + 1 s n + 2 s n + 5 h n + 5 s n + 6 h n + 6 s n + 7 h n + 7 s n + 8 h n + 8 b 1 , n - 1 b 1 , n b 1 , n + 1 b 1 , n + 4 b 1 , n + 5 b 1 , n + 6 b 1 , n + 7 b 2 , n - 2 b 2 , n - 1 b 2 , n b 2 , n + 4 b 2 , n + 5 b 2 , n + 6 b 9 , n - 5 b 9 , n - 4 b 9 , n b 9 , n + 1 b 9 , n + 2 b 9 , n + 3 t lat t od t h data n-1 data n clock input data output 1.5v t ap analog input t aj 1.5v 2.4v 0.5v HI5662
3-9 typical performance curves figure 3. effective number of bits (enob) and sinad vs input frequency figure 4. snr vs input frequency figure 5. -thd, -2hd and -3hd vs input frequency figure 6. sinad, snr and -thd vs input amplitude figure 7. effective number of bits (enob) vs sample clock duty cycle figure 8. supply current vs sample clock frequency 8 7 6 5 50 44 38 32 sinad (db) enob (bits) 1 10 100 input frequency (mhz) f s = 60msps t a = 25 o c 50 44 38 32 1 10 100 snr (db) input frequency (mhz) f s = 60msps t a = 25 o c 90 60 55 50 1 10 100 input frequency (mhz) f s = 60msps t a = 25 o c 85 80 75 70 65 -3hd -thd -2hd dbc 30 20 10 db input level (dbfs) 70 60 50 40 -40 -10 0 -30 -20 snr (db) or sinad (db) -thd (dbc) duty cycle (%, t hi /t clk ) 42 44 46 48 50 52 54 40 enob (bits) 5 6 7 8 56 58 60 f s = 60msps 1mhz < f in < 15mhz t a = 25 o c f s (msps) 30 40 50 60 70 20 supply current (ma) 0 10 30 40 50 60 70 20 10 100 110 120 130 140 90 80 150 1mhz < f in < 15mhz t a = 25 o c i cc ai cc di cc1 di cc2 di cc3 HI5662
3-10 figure 9. internal reference voltage (v rout )vs temperature figure 10. dc bias voltage (i/qvdc) vs temperature figure 11. data output delay (t od ) vs temperature figure 12. supply current vs temperature figure 13. 2048 point fft plot typical performance curves (continued) temperature ( o c) 0 20406080 -20 internal reference voltage, 2.40 -40 2.43 2.44 2.45 2.46 2.47 2.42 2.41 2.50 2.49 2.48 v rout (v) temperature ( o c) 0 20406080 -20 dc bias voltage, i/q v dc (v) -40 2.85 2.90 2.95 3.10 3.05 3.00 qv dc iv dc temperature ( o c) 0 20406080 -20 t od (ns) -40 11.0 11.5 13.0 12.5 12.0 t od temperature ( o c) 0 20406080 -20 supply current (ma) -40 0 20 80 60 40 100 120 140 f s = 60msps 1mhz < f in < 15mhz di cc2 i cc ai cc di cc1 di cc3 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 db 0 100 200 300 400 500 600 700 800 900 1023 frequency (bin) f s = 60msps f in = 10mhz t a = 25 o c HI5662
3-11 detailed description theory of operation the HI5662 is a dual 8-bit fully differential sampling pipeline a/d converter with digital error correction logic. figure 14 depicts the circuit for the front end differential-in-differential- out sample-and-hold (s/h) ampli?rs. the switches are controlled by an internal sampling clock which is a non- overlapping two phase signal, 1 and 2 , derived from the master sampling clock. during the sampling phase, 1 , the input signal is applied to the sampling capacitors, c s . at the same time the holding capacitors, c h , are discharged to analog ground. at the falling edge of 1 the input signal is sampled on the bottom plates of the sampling capacitors. in the next clock phase, 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. the charge then redistributes between c s and c h completing one sample-and-hold cycle. the front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. the circuit not only performs the sample- and-hold function but will also convert a single-ended input to a fully-differential output for the converter core. during the sampling phase, the i/q in pins see only the on-resistance of a switch and c s . the relatively small values of these components result in a typical full power input bandwidth of 250mhz for the converter. as illustrated in the functional block diagram and the timing diagram in figure 1, identical pipeline subconverter stages, each containing a two-bit ?sh converter and a two-bit multiplying digital-to-analog converter, follow the s/h circuit with the last stage being a two bit ?sh converter. each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. the output of each of the identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. the output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. the function of the digital delay line is to time align the digital outputs of the identical two-bit subconverter stages with the corresponding output of the last stage ?sh converter before applying the results to the digital error correction logic. the digital error correction logic uses the supplementary bits to correct any error that may exist before generating the ?al eight bit digital data output of the converter. because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clock after the analog sample is taken (see the timing diagram in figure 1). this time delay is speci?d as the data latency. after the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. the digital output data is provided in offset binary format (see table 1, a/d code table). internal reference voltage output, v refout the HI5662 is equipped with an internal reference voltage generator, therefore, no external reference voltage is required. v rout must be connected to v rin when using the internal reference voltage. table 1. a/d code table code center description differential input voltage (i/q in + - i/q in -) offset binary output code msb lsb i/qd7 i/qd6 i/qd5 i/qd4 i/qd3 i/qd2 i/qd1 i/qd0 +full scale (+fs) - 7 / 16 lsb 0.498291v 11111111 +fs - 1 7 / 16 lsb 0.494385v 11111110 + 9 / 16 lsb 2.19727mv 10000000 - 7 / 16 lsb -1.70898mv 01111111 -fs + 1 9 / 16 lsb -0.493896v 00000001 -full scale (-fs) + 9 / 16 lsb -0.497803v 00000000 note: 8. the voltages listed above represent the ideal center of each output code shown with v refin = +2.5v. - + + - c h c s c s c h i/q in+ v out+ v out- i/q in- 1 1 1 2 1 1 1 figure 14. analog input sample-and-hold HI5662
3-12 an internal band-gap reference voltage followed by an ampli?r/buffer generates the precision +2.5v reference voltage used by the converter. a band-gap reference circuit is used to generate a precision +1.25v internal reference voltage. this voltage is then ampli?d by a wide-band uncompensated operational ampli?r connected in a gain-of-two con?uration. an external, user-supplied, 0.1 f capacitor connected from the v rout output pin to analog ground is used to set the dominant pole and to maintain the stability of the operational ampli?r. reference voltage input, v refin the HI5662 is designed to accept a +2.5v reference voltage source at the v rin input pin. typical operation of the converter requires v rin to be set at +2.5v. the HI5662 is tested with v rin connected to v rout yielding a fully differential analog input voltage range of 0.5v. the user does have the option of supplying an external +2.5v reference voltage. as a result of the high input impedance presented at the v rin input pin, 1.25k ? typically, the external reference voltage being used is only required to source 2ma of reference input current. in the situation where an external reference voltage will be used an external 0.1 f capacitor must be connected from the v rout output pin to analog ground in order to maintain the stability of the internal operational ampli?r. in order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, v rin . analog input, differential connection the analog input of the HI5662 is a differential input that can be con?ured in various ways depending on the signal source and the required level of performance. a fully differential connection (figure 15 and figure 16) will deliver the best performance from the converter. since the HI5662 is powered by a single +5v analog supply, the analog input is limited to be between ground and +5v. for the differential input connection this implies the analog input common mode voltage can range from 0.25v to 4.75v. the performance of the adc does not change signi?antly with the value of the analog input common mode voltage. a dc voltage source, i/qv dc , equal to 3.0v (typical), is made available to the user to help simplify circuit design when using an ac coupled differential input. this low output impedance voltage source is not designed to be a reference but makes an excellent dc bias source and stays well within the analog input common mode voltage range over temperature. for the ac coupled differential input (figure 15) and with v rin connected to v rout , full scale is achieved when the v in and -v in input signals are 0.5v p-p , with -v in being 180 degrees out of phase with v in . the converter will be at positive full scale when the i/q in + input is at v dc + 0.25v and the i/q in- input is at v dc - 0.25v (i/q in+ - i/q in- = +0.5v). conversely, the converter will be at negative full scale when the i/q in+ input is equal to v dc - 0.25v and i/q in- is at v dc + 0.25v (i/q in+ - i/q in- = -0.5v). the analog input can be dc coupled (figure 16) as long as the inputs are within the analog input common mode voltage range (0.25v vdc 4.75v). the resistors, r, in figure 16 are not absolutely necessary but may be used as load setting resistors. a capacitor, c, connected from i/q in + to i/q in - will help ?ter any high frequency noise on the inputs, also improving performance. values around 20pf are suf?ient and can be used on ac coupled inputs as well. note, however, that the value of capacitor c chosen must take into account the highest frequency component of the analog input signal. analog input, single-ended connection the con?uration shown in figure 17 may be used with a single ended ac coupled input. again, with v rin connected to v rout , if v in is a 1v p-p sinewave, then i/q in+ is a 1.0v p-p sinewave riding on a positive voltage equal to v dc . the converter will be at positive full scale when i/q in+ is at v dc + 0.5v (i/q in+ - i/q in- = +0.5v) and will be at negative full scale when i/q in+ is equal to v dc - 0.5v (i/q in+ - i/q in- = -0.5v). sufficient headroom must be provided such that the input voltage never goes above +5v i/q in + i/qv dc i/q in - HI5662 v in -v in r r figure 15. ac coupled differential input i/q in + i/qv dc i/q in - HI5662 v in -v in r r c v dc v dc figure 16. dc coupled differential input i/q in + i/q in - HI5662 v in v dc r figure 17. ac coupled single ended input HI5662
3-13 or below agnd. in this case, v dc could range between 0.5v and 4.5v without a significant change in adc performance. the simplest way to produce v dc is to use the dc bias source, i/qv dc , of the HI5662. the single ended analog input can be dc coupled (figure 18) as long as the input is within the analog input common mode voltage range. the resistor, r, in figure 18 is not absolutely necessary but may be used as a load setting resistor. a capacitor, c, connected from i/q in + to i/q in - will help ?ter any high frequency noise on the inputs, also improving performance. values around 20pf are suf?ient and can be used on ac coupled inputs as well. note, however, that the value of capacitor c chosen must take into account the highest frequency component of the analog input signal. a single ended source may give better overall system performance if it is ?st converted to differential before driving the HI5662. sampling clock requirements the HI5662 sampling clock input provides a standard high- speed interface to external ttl/cmos logic families. in order to ensure rated performance of the HI5662, the duty cycle of the clock should be held at 50% 5%. it must also have low jitter and operate at standard ttl/cmos levels. performance of the HI5662 will only be guaranteed at conversion rates above 1msps (typ). this ensures proper performance of the internal dynamic circuits. similarly, when power is ?st applied to the converter, a maximum of 20 cycles at a sample rate above 1msps must to be performed before valid data is available. supply and ground considerations the HI5662 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. the digital data outputs also have a separate supply pin, dv cc3 , which can be powered from a 3.0v or 5.0v supply. this allows the outputs to interface with 3.0v logic if so desired. the part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. for best performance, the supplies to the HI5662 should be driven by clean, linear regulated supplies. the board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. if the part is powered off a single supply then the analog supply can be isolated by a ferrite bead from the digital supply. refer to the application note ?sing intersil high speed a/d converters?(an9214) for additional considerations when using high speed converters. static performance de?itions offset error (v os ) the midscale code transition should occur at a level 1 / 4 lsb above half-scale. offset is de?ed as the deviation of the actual code transition from this point. full-scale error (fse) the last code transition should occur for an analog input that is 3 / 4 lsb below positive full scale (+fs) with the offset error removed. full scale error is de?ed as the deviation of the actual code transition from this point. differential linearity error (dnl) dnl is the worst case deviation of a code width from the ideal value of 1lsb. integral linearity error (inl) inl is the worst case deviation of a code center from a best ? straight line calculated from the measured data. power supply sensitivity each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error (in lsbs) is noted. dynamic performance de?itions fast fourier transform (fft) techniques are used to evaluate the dynamic performance of the HI5662. a low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in ram. the data is then transformed into the frequency domain with an fft and analyzed to evaluate the dynamic performance of the a/d. the sine wave input to the part is typically -0.5db down from full scale for all these tests. snr and sinad are quoted in db. the distortion numbers are quoted in dbc (decibels with respect to carrier) and do not include any correction factors for normalizing to full scale. the effective number of bits (enob) is calculated from the sinad data by: enob = (sinad - 1.76 + v corr ) / 6.02, where: v corr = 0.5db (typical). v corr adjusts the sinad, and hence the enob, for the amount the analog input signal is backed off from full scale. i/q in + i/q in - HI5662 v dc r c v in v dc figure 18. dc coupled single ended input HI5662
3-14 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com signal to noise and distortion ratio (sinad) sinad is the ratio of the measured rms signal to rms sum of all the other spectral components below the nyquist frequency, f s /2, excluding dc. signal to noise ratio (snr) snr is the ratio of the measured rms signal to rms noise at a speci?d input and sampling frequency. the noise is the rms sum of all of the spectral components below f s /2 excluding the fundamental, the ?st ?e harmonics and dc. total harmonic distortion (thd) thd is the ratio of the rms sum of the first 5 harmonic components to the rms value of the fundamental input signal. 2nd and 3rd harmonic distortion this is the ratio of the rms value of the applicable harmonic component to the rms value of the fundamental input signal. spurious free dynamic range (sfdr) sfdr is the ratio of the fundamental rms amplitude to the rms amplitude of the next largest spectral component in the spectrum below f s /2. intermodulation distortion (imd) nonlinearities in the signal path will tend to generate intermodulation products when two tones, f 1 and f 2 , are present at the inputs. the ratio of the measured signal to the distortion terms is calculated. the terms included in the calculation are (f 1 +f 2 ), (f 1 -f 2 ), (2f 1 ), (2f 2 ), (2f 1 +f 2 ), (2f 1 -f 2 ), (f 1 +2f 2 ), (f 1 -2f 2 ). the adc is tested with each tone 6db below full scale. transient response transient response is measured by providing a full-scale transition to the analog input of the adc and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. over-voltage recovery over-voltage recovery is measured by providing a full-scale transition to the analog input of the adc which overdrives the input by 200mv, and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. full power input bandwidth (fpbw) full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3db below the amplitude of the input sine wave. the input sine wave has an amplitude which swings from -fs to +fs. the bandwidth given is measured at the speci?d sampling frequency. i/q channel crosstalk i/q channel crosstalk is a measure of the amount of channel separation or isolation between the two a/d converter cores contained within the dual converter package. the measurement consists of stimulating one channel of the converter with a fullscale input signal and then measuring the amount that signal is below, in dbc, a fullscale signal on the opposite channel. timing de?itions refer to figure 1 and figure 2 for these de?itions. aperture delay (t ap ) aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. this delay is due to internal clock path propagation delays. aperture jitter (t aj ) aperture jitter is the rms variation in the aperture delay due to variation of internal clock path delays. data hold time (t h ) data hold time is the time to where the previous data (n - 1) is no longer valid. data output delay time (t od ) data output delay time is the time to where the new data (n) is valid. data latency (t lat ) after the analog sample is taken, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clock after the analog sample is taken. this is due to the pipeline nature of the converter where the analog sample has to ripple through the internal subconverter stages. this delay is speci?d as the data latency. after the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. the digital data lags the analog input sample by 6 sample clock cycles. power-up initialization this time is de?ed as the maximum number of clock cycles that are required to initialize the converter at power-up. the requirement arises from the need to initialize the dynamic circuits within the converter. HI5662

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